ELECTRA: a timing verifier, static checker and power estimator for nMOS circuits.

摘要

As the complexity of integrated circuits increases, new design methodologies andtools have to be developed to manage such projects. In this thesis, a three-in-oneverification tool (ELECTRA) for nMOS circuits is proposed.At the heart of ELECTRA, is a data independent timing verifier which can beused to locate critical paths in nMOS circuits, and provide performance analysis ofcircuits comparable to that obtained using circuit simulators. The use of Bryant’snetwork model to represent the circuit to be analysed, simplifies the problem ofanalysing a circuit to that of analysing a number of sub-circuits in which only localinteractions need to be considered. The timing verifier uses a depth-first searchtechnique to traverse the circuit to be analysed. Delay estimations in the timingverifier are based on RC modeling of transistor networks. Currently, three RC delaymodels ( the modified lumped RC, linear RC and RC tree ) of different complexityand accuracy are supported by ELECTRA, to estimate the delays involved in eachsub-circuit.The static checker component of ELECTRA can be used to detect anyviolations of 4:1 and 8:1 pull-up/pull-down ratios design rule. It is also capable ofdetecting any threshold voltage drops involving a pass transistor driving the gate ofanother pass transistor.Power estimations in digital nMOS circuits can be obtained using the powerestimator provided in ELECTRA. Computation of power involved is based onsimple assumptions about the circuit being analysed.