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Operational amplifier with high common mode rejection
Operational amplifier with high common mode rejection
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机译:具有高共模抑制比的运算放大器
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摘要
An operational amplifier includes a symmetrical end stage being formed of emitter followers. The end stage has output terminals forming outputs of the operational amplifier and has input terminals. A voltage divider is connected between the output terminals of the end stage and has a tap. A first differential amplifier stage has input terminals forming symmetrical inputs of the operational amplifier and has output terminals each being coupled to a respective one of the input terminals of the end stage. Loads each terminate a respective one of the output terminals of the first differential amplifier stage. Two second parallel- connected differential amplifier stages each have a first input terminal connected to a reference potential, a second input terminal connected to the tap of the voltage divider, and an output terminal each being coupled to a respective one of the loads.
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