Method and apparatus for merging hierarchical test subsequence and finite state machine (FSM) model graphs

摘要

Hierarchical Test Subsequence (TS) subgraphs and Finite State Machine (FSM) subgraphs are merged.PPHierarchical FSM subgraphs are merged (82) by connecting FSM model (33) child subgraph transitions or graph edges with states or vertices in the FSM parent subgraph. Matching is done based on Input/Output sequences. This merging (82) is repeated until all FSM child subgraphs are merged into FSM childless subgraphs. FSM childless subgraphs are Merged FSM graphs (83). P PHierarchical Test Subsequence (TS) subgraphs (65) are merged (38) by finding peer subgraphs for TS child subgraphs. TS micro- edges from module entry and to module exit are connected to peer level FSM model states or vertices identified by matching Input/Output sequences. This merging (38) is repeated until all TS child subgraphs are merged into TS childless subgraphs. TS childless subgraphs are Merged TS graphs (39).