Overvoltage-tolerant self-biasing CMOS output buffer

摘要

An overvoltage-tolerant self-biasing input/output buffer circuit having a p-channel field-effect transistor ("FET"), a first n- channel FET and a biasing circuit for biasing the body of the p-channel FET so as to prevent forward-biasing of the of the p-channel FET. The p- channel FET has a source connected to a first voltage, a gate connected to a first input, a drain connected to an output, and the body connected to a node. The first n-channel FET has a drain connected to the output, a gate connected to a second input, a body connected to a second voltage, and a source connected to the second voltage. The biasing circuit includes a second n-channel FET and a third n-channel FET. The second n- channel FET has a source and a gate connected to the first voltage, a drain connected to the node, and a body connected to the second voltage. The third n- channel FET has a drain connected to the node, a gate and a source connected to the output, and a body connected to the second voltage.