首页> 外国专利> Method of employing multi-layer tab tape in semiconductor device assembly by selecting, breaking, downwardly bending and bonding tab tape trace free ends to a ground or power plane

Method of employing multi-layer tab tape in semiconductor device assembly by selecting, breaking, downwardly bending and bonding tab tape trace free ends to a ground or power plane

机译:通过选择,断裂,向下弯曲并将接线片带迹线的自由端选择,断开,向下弯曲并将其粘结到接地或电源平面上的方法,在半导体器件组件中采用多层接线片带方法

摘要

One or two, or more, additional conductive layers, separated from one another (if two or more) and separated from a patterned (signal) conductive layer are formed in a flexible substrate, for mounting a semiconductor die in a semiconductor device assembly. These additional layers are used as separate planes for carrying power and/or ground from outside the assembly to the die, on a separate plane from signals entering or exiting the die. Another aspect of the present invention provides a semiconductor device assembly including a first conductive layer with a plurality of traces formed on an insulating layer, a second conductive layer with an inner edge portion exposed within the central opening in the insulating layer, and a leadframe having a number of leads the inner end of one or more of the leads being electrically connected to an outer end of one or more of the traces. Selected traces are cut substantially at an inner peripheral edge of the first insulating layer, bent past the first insulating layer, and bonded to the exposed inner edge portion of the second conductive layer. The insulating layer may also include an outer peripheral opening through which an outer edge portion of the second conductive layer is exposed. The selected traces are cut substantially at the inner edge of the outer peripheral opening in the insulating layer, bent past the insulating layer, and bonded to the outer edge portion of the second conductive layer.
机译:在柔性基板中形成彼此分开(如果两个或更多个)并且与图案化(信号)导电层分开的一个或两个或更多附加导体层,用于将半导体管芯安装在半导体器件组件中。这些额外的层用作从组件外部将功率和/或接地从裸片携带到裸片的单独平面,在进入或离开裸片的信号的单独平面上。本发明的另一方面提供了一种半导体器件组件,其包括:第一导电层,其在绝缘层上形成有多个迹线;第二导电层,其内边缘部分暴露在绝缘层的中心开口内;以及引线框架,其具有多个引线中的一个或多个引线的内端电连接到一个或多个迹线的外端。所选择的迹线基本上在第一绝缘层的内周边缘处被切割,弯曲越过第一绝缘层,并结合到第二导电层的暴露的内边缘部分。绝缘层还可包括外围开口,第二导电层的外边缘部分通过该外围开口暴露。所选择的迹线基本上在绝缘层中的外围开口的内边缘处被切割,弯曲越过绝缘层,并结合到第二导电层的外边缘部分。

著录项

  • 公开/公告号US5638596A

    专利类型

  • 公开/公告日1997-06-17

    原文格式PDF

  • 申请/专利权人 LSI LOGIC CORPORATION;

    申请/专利号US19950462194

  • 发明设计人 JOHN MCCORMICK;

    申请日1995-06-05

  • 分类号H01R43/00;H05K3/30;

  • 国家 US

  • 入库时间 2022-08-22 03:09:58

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