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Integrated circuit chip having built-in self measurement for PLL jitter and phase error
Integrated circuit chip having built-in self measurement for PLL jitter and phase error
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机译:具有用于PLL抖动和相位误差的内置自测量功能的集成电路芯片
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摘要
A built-in system and method is provided that measures Phase Lock Loop (PLL) output clock error. An edge sorting circuit is utilized to measure jitter between corresponding transition edges of a measured clock and a reference clock, and then stores the value in an N bit word. A decoder circuit reads in the value and increments a corresponding counter. A state machine then reads the counters, processes the information and outputs one or more PLL clock error values.
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