This paper discusses the development of a new type of BIST circuit, the (VDL)2, with the purpose of measuring jitter in IBM's phase locked loops. The (VDL)2, which stands for Variable Vernier Digital Delay Locked Line, implements both cycle-to-cycle and phase jitter measurements, by using a digital delay locked loop and a 60 stage Vernier delay line. This achieves a nominal jitter resolution of 10 ps with a capture range of +/- 150 ps and does so in real time. The proposed application for this circuit is during manufacturing test of the PLL. The circuit is implemented in IBM's 90 nm process and was completed in the PLL and Clocking Development ASIC group at IBM Microelectronics in Essex Junction, Vermont as part of the VI-A program.
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机译：本文讨论了新型BIST电路（VDL）2的开发，其目的是测量IBM锁相环中的抖动。 （VDL）2代表可变游标数字延迟锁定线，它通过使用数字延迟锁定环路和60级游标延迟线来实现周期到周期和相位抖动的测量。这样可以实现10 ps的标称抖动分辨率，捕获范围为+/- 150 ps，并且可以实时进行。该电路的建议应用是在PLL的制造测试期间。该电路以IBM的90 nm工艺实现，并由VI-A计划的一部分由位于佛蒙特州埃塞克斯路口的IBM Microelectronics的PLL和Clocking Development ASIC组完成。
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