首页>
外国专利>
Fault tolerant computer memory systems and components employing dual level error correction and detection with disablement feature
Fault tolerant computer memory systems and components employing dual level error correction and detection with disablement feature
展开▼
机译:容错计算机存储系统和组件,采用具有禁用功能的双级错误纠正和检测
展开▼
页面导航
摘要
著录项
相似文献
摘要
In a memory system comprising a plurality of memory units each of which possesses unit-level error correction capabilities and each of which is tied to a system level error correction function, memory reliability is enhanced by providing a mechanism for disabling the unit- level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
展开▼