FAULT TOLERANT COMPUTER MEMORY SYSTEMS AND COMPONENTS EMPLOYING DUAL LEVEL ERROR CORRECTION AND DETECTION WITH DISABLEMENT FEATURE

摘要

In a memory system comprising a plurality of memory units (10) each of whichpossesses unit-level error correction capabilities (20) and each of which are -tied to a systemlevel error correction function (30), memory reliability is enhanced by providing means(Fig.2) for disabling the unit-level error correction capability, for example, in response to theoccurrence of an uncorrectable error in one of the memory units. This counter-intuitiveapproach which disables an error correction function nonetheless enhances overall memorysystem reliability since it enables the employment of the complement/recomplement algorithmwhich depends upon the presence of reproducible errors for proper operation. Thus, chiplevel error correction systems, which are increasingly desirable at high packaging densities,are employed in a way which does not interfere with system level error correction methods.