PSEUDO RANDOM PATTERN ERROR MEASURING CIRCUIT

摘要

PROBLEM TO BE SOLVED: To reduce a circuit scale, reduce a mounting area and to realize a high speed operation by means of shorting delay time between elements by preventing circuits outputting the PN patterns of reference from becoming proportional to the number (n) of the bits of parallel signals. ;SOLUTION: Respective flip flop circuits 4-1 to 4-N output the sampled PN patterns of respective n-th bits with the operation result by (n-N+1) to n-bit post operation circuits 6-(n-N+1) to 6-n as a base by setting PN(1)-PN(N) as initial values. The comparison of reception data and the PN patterns of reference is executed by comparing data obtained by delaying reception data in a delay circuit 7 with the PN pattern of reference. Namely, the comparison of first to N-th buts is the comparison of the outputs of the flip flop circuits 4-1 to 4-N with the first to N-th bits of reception data outputted from the delay circuit 7. The comparison of (N+1)-th to n-th bits is executed by the comparison of the outputs of the operation circuit 6-1 to 6-(n-N) and (N+1)-th bits to n-th bits, which are outputted from the delay circuit 7.;COPYRIGHT: (C)1998,JPO