PROBLEM TO BE SOLVED: To provide the phase locked loop(PLL) circuit that is suitable for adjusting an input signal with data coded by a different sampling frequency. ;SOLUTION: The self-tuning clock recovery PLL includes a programmable 1/M division circuit 101, a phase frequency detector 102, a programmable voltage controlled oscillator(VCO) 105, a programmable 1/N division circuit 107, and a PLL tuning circuit and executes the similar operation to that by a conventional PLL in the usual mode. However, a frequency of an input clock signal to the PLL is largely changed from a threshold level, the PLL tuning circuit adjusts an offset and a gain parameter of the PLL to turn a new frequency to the PLL again. When an output clock frequency of the PLL is nearly equal to an input clock frequency multiplied with a closed loop gain of the PLL, since an input voltage to the VCO 105 is in the middle of the input voltage range, the VCO 105 is operated in a linear region over a wide frequency range.;COPYRIGHT: (C)1998,JPO
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