MULTIPROCESSOR DEVICE AND ITS MEMORY ACCESS METHOD, TRANSMISSION DEVICE AND RECEPTION DEVICE OF DATA TRANSFER SYSTEM, AND DATA TRANSFER SYSTEM AND ITS BUS CONTROL METHOD

摘要

PROBLEM TO BE SOLVED: To shorten the processing time of the multiprocessor device which has processor devices connected through a system bus by decreasing the frequency of issue of a cache invalidation command for a cache memory. SOLUTION: This multiprocessor device 10 is equipped with processor groups 1-1 to 1-n having at least =1 processors 2-1 to 2-n, a main storage memory 7, cache memories 3-1 to 3-m, cache control parts 4-1 to 4-m, a directory memory 8, and a directory control part 9. In this case, the directory control part 9 is equipped with an invalidation command issue part 9a which issues invalidation commands for cache lines, one by one, to all reference destinations stored in the directory memory 8.