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Pseudo error reduction crosstalk verification manner and system

机译:伪差错串扰验证方法及系统

摘要

PROBLEM TO BE SOLVED: To prevent and reduce the handling of a signal passage to be invalid as an error by previously and automatically extracting a part to be invalid in operation so as to verify the crosstalk of a logical circuit based on this extracted information. ;SOLUTION: This system consists of an assembler instruction string storing means 1, a verification unnecessary polarity extracting means 2, a verification unnecessary polarity storing means 3, a model storing means 4, a model correcting means 5, a corrected model storing means 6 and a crosstalk verifying means 7. One or plural signal transitions which can not be generated at a signal terminal at a pattern string are previously and automatically extracted from the pattern string driving the logical circuit of the object of crosstalk verification to the prescribed signal terminal of the logical circuit inputting the pattern string. Then, at the time of crosstalk-analyzing a signal wire which is estimated to be affected by a signal wire connected to the prescribed signal terminal, the extracted signal transition is removed from the objects of crosstalk analysis to verify crosstalk.;COPYRIGHT: (C)1997,JPO
机译:要解决的问题:通过事先自动地提取出工作中无效的部分,从而基于提取的信息来验证逻辑电路的串扰,从而防止并减少信号通道作为错误而无效的处理。 ;解决方案:该系统由一个汇编程序指令字符串存储装置1,一个不需要验证的极性提取装置2,一个不需要验证的极性存储装置3,一个模型存储装置4,一个模型校正装置5,一个经过校正的模型存储装置6和预先并自动地从将串扰验证的对象的逻辑电路驱动到串扰验证对象的逻辑电路的模式串中提取在串模式的信号端子处不能产生的一个或多个信号转换。逻辑电路输入模式字符串。然后,在对被估计受连接到指定信号端子的信号线影响的信号线进行串扰分析时,从串扰分析的对象中删除提取的信号过渡以验证串扰。 1997年,日本特许厅

著录项

  • 公开/公告号JP2792485B2

    专利类型

  • 公开/公告日1998-09-03

    原文格式PDF

  • 申请/专利权人 NIPPON DENKI KK;

    申请/专利号JP19950297890

  • 发明设计人 HASEGAWA TAKUMI;

    申请日1995-10-20

  • 分类号G06F17/50;

  • 国家 JP

  • 入库时间 2022-08-22 03:01:18

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