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Uses the phase simulation circuit and the said phase simulation circuit the phase simulation manner

机译:采用相位仿真电路和所述相位仿真电路的相位仿真方式

摘要

PROBLEM TO BE SOLVED: To establish a synchronization state in a short time by using a clock error detection circuit and a control voltage comparator circuit so as to detect whether an input clock is normal or in error. ;SOLUTION: A VCO control voltage outputted from a phase comparator circuit 11 is given to an LPF 12, in which a high frequency component is eliminated and the resulting voltage is outputted as a control voltage (a). The control voltage (a) is given to an A/D converter circuit 13 and a selection circuit 16. A clock error detection circuit 19 detects a state of an input clock and gives the error detection signal to a memory circuit 14 and the selection circuit 16. When it is discriminated that the input clock restores from the erroneous state to the normal state, a control voltage (b) outputted from the A/D converter circuit 13 is compared with a control voltage (c) outputted from the memory circuit 14 by a control voltage comparator circuit 20. When they are not equal to each other, a phase of an output clock from a VCO 17 controlled by a control voltage (d) is controlled by a frequency divider circuit 18.;COPYRIGHT: (C)1997,JPO
机译:解决的问题:通过使用时钟错误检测电路和控制电压比较器电路在短时间内建立同步状态,以便检测输入时钟是正常还是错误。 ;解决方案:将从相位比较器电路11输出的VCO控制电压提供给LPF 12,在该LPF 12中消除了高频分量,并且将所得电压作为控制电压(a)输出。控制电压(a)被提供给A / D转换器电路13和选择电路16。时钟错误检测电路19检测输入时钟的状态,并将错误检测信号提供给存储电路14和选择电路。 16.当辨别输入时钟从错误状态恢复到正常状态时,将从A / D转换器电路13输出的控制电压(b)与从存储电路14输出的控制电压(c)进行比较。通过控制电压比较器电路20,当它们彼此不相等时,由分压电路18控制由控制电压(d)控制的VCO 17的输出时钟的相位。;版权:(C) 1997年

著录项

  • 公开/公告号JP2728069B2

    专利类型

  • 公开/公告日1998-03-18

    原文格式PDF

  • 申请/专利权人 NIPPON DENKI KK;

    申请/专利号JP19950333176

  • 发明设计人 OKABAYASHI TETSUYA;

    申请日1995-12-21

  • 分类号H03L7/14;H03L7/199;

  • 国家 JP

  • 入库时间 2022-08-22 03:00:40

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