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The design and simulations of phase and timing tracking circuits with pre-assured 2nd order digital loop filter

机译:预先确定的二阶二阶数字环路滤波器的相位和时序跟踪电路的设计和仿真

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摘要

Phase and timing tracking circuits are always a crucial issue in circuit designs, especially in mobile communications and many other applications which will produce phase shift or timing jitter due to relative activity or environments variations. For keeping track of these crucial changing parameters, a synchronization circuit with 2nd order digital loop is generally applied for its simplicity, flexibility, and fast setting time. In this paper, a typical 2nd order digital loop filter with pre-assured stable convergence triangle from Jury criteria is developed, which can then be directly applied in many circuit designs with phase or timing jitter by simply adjusting two digital loop parameters. The convergence property and the effectiveness of this digital loop filter and its applied circuits with derived recursive formulations are well studied and simulated. This simple and direct scheme can easily tell the designers the stable convergence contours under specific circumstances in the whole design stages.
机译:相位和时序跟踪电路一直是电路设计中的关键问题,尤其是在移动通信和许多其他应用中,由于相对活动或环境变化,这些应用会产生相移或时序抖动。为了跟踪这些关键的变化参数,通常使用具有2阶数字环路的同步电路,因为其简单,灵活且设置时间短。本文根据Jury准则开发了一种典型的具有二次保证稳定收敛三角的2阶数字环路滤波器,然后可以通过简单地调整将其直接应用于许多具有相位或时序抖动的电路设计中两个数字回路参数。对该数字环路滤波器及其应用电路与递归公式的收敛性和有效性进行了很好的研究和仿真。这种简单直接的方案可以轻松地告诉设计人员在整个设计阶段中特定情况下的稳定收敛轮廓。

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