PURPOSE:To make the operation of a relevant circuit stable by controlling a 4-bit counter with an output of a rising detection circuit for a 64Kbit/sec data, generating a 64kHz clock, allowing the 4-bit counter to count independently even if the 64Kbit/sec data is interrupted so as to generate a 64kHz clock. CONSTITUTION:A clock is not directly extracted from a 64Kbit/sec data but a 4-bit counter 4 being other clock source is controlled by an output of a rising detection circuit 3 for the 64Kbit/sec data to generate a 64kHz clock. Even if the 64Kbit/sec data is interrupted, the 4-bit counter 4 counts the number independently to generate the 64kHz clock. That is, even if the 64Kbit/sec data S1 is interrupted at a moment, so long as the 4-bit counter 4 receives a clock of 2.048MHz, the 64kHz clock is outputted. Thus, the stable operation of the relevant circuit is warranted.
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