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RANGKAIAN TERPADU SEMIKONDUKTOR DAN SISTEM YANG MENGGUNAKAN RANGKAIAN TERSEBUT

机译:使用该网络的集成网络半导体和系统

摘要

PROBLEM TO BE SOLVED: To reduce to the minimum the increase in chip area and the influence of increase in wiring delay by a method in which a plurality of terminal cells have a connection part to be used for mediation of communication between a semiconductor integrated circuit and one of a plurality of substrate cells. ;SOLUTION: A plurality of data columns 12 contain plural fundamental cells 20 and at least a terminal cell 22. Fundamental cells 20a and the terminal cells 22a, to be connected to the fundamental cells 20a, are adjacently arranged in the same data column 12, and fundamental cell 20b and the terminal cell 22b, to be connected to the fundamental cell 20b, are adjacently arranged in the same column 12. As a result, a module is formed by laminating a semiconductor integrated circuit and other semiconductor integrated circuit. By this lamination, a plurality of kinds of semiconductor integrated circuits and by changing a part (connection layer) of the other semiconductor integreated circuit, a plurality of kinds of semiconductor integrated circuits can be interfaced. As a result, the developing manhours of the module can be decreased.;COPYRIGHT: (C)1998,JPO
机译:解决的问题:通过使多个端子单元具有用于介导半导体集成电路与半导体之间的通信的连接部的方法,将芯片面积的增加和布线延迟的增加的影响减小到最小。多个基底单元之一。 ;解决方案:多个数据列12包含多个基本单元20和至少一个终端单元22。基本单元20a和要连接到基本单元20a的终端单元22a相邻布置在同一数据列12中。而且,与基本单元20b连接的基本单元20b和端子单元22b在同一列12中相邻配置。其结果,通过层叠半导体集成电路和其他半导体集成电路来形成模块。通过该层压,可以使多种半导体集成电路和通过改变另一半导体集成电路的一部分(连接层)而使多种半导体集成电路相接。结果,可以减少模块的开发工时。;版权所有:(C)1998,日本特许厅

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