Parallel multi-phased amorphous silicon shift register for fast addressing of an amorphous silicon array

摘要

A shift register assembly having an integrated multi-phased dynamic shift register (50) with a corresponding multi-phased driving buffer (60) for addressing elements of an array. The shift register and buffer combination is used to select segments on the array having a common select line (VG)thus reducing the number of input lines needed to address such an array. Furthermore, the multi-phased operation of the shift register allows for faster operation than that of a traditional shift register setup.