Matching and Synchronization of Asymmetric Single-Chip Dual Multiprocessors

摘要

An integrated multiprocessor architecture has been disclosed that simplifies synchronization of multiple processing devices. The multiprocessor comprises a general purpose processor and a vector processor having a single instruction multiple data scheme. All multiprocessors in the vector processor process instructions concurrently and do not require software synchronization. The general purpose processor controls the vector processor and also operates the vector processor to form a fork in the program flow. The two processors execute the program in parallel until the control processor stops the vector processor or until an exception occurs, or until the vector processor completes the program and enters the idle state. A register coupled to both processors for accessing both processors stores a status bit indicating whether the vector processor is in an operating state or an idle state. The general purpose processor synchronizes the separate programs by executing a loop that polls the status bits. When the status bit indicates the idle state of the vector processor, the general purpose processor processes the results from the vector processor and restarts the vector processor.