Special hardware and software for testing SIMMs manufactured using noncompactant memory chips

摘要

The test system of the SIMM memory module assembled using the faulty memory chip according to the present invention has 32 bits from the data bus in the reference write phase in order to verify the failure rate and its associated address. A pattern register 10 having a 48 bit output to a pattern inverter 11 having a 48 bit output Dout and a data register 14 connected to a data comparator 14 in a comparison write phase, Via a comparator, a circuit comprising a pattern inverter 13 with a 48 bit input (Din) connected to an error coder with a 32 bit output to a data bus.