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Integrated circuit memory device with embedded self-test circuitry with monitor and tester modes

机译:具有嵌入式自检电路的集成电路存储设备,具有监控器和测试器模式

摘要

The integrated circuit memory device 10 of the present invention is provided with a self test monitor mode. The memory device 10 includes a memory array 26 having a plurality of memory cells. The memory device (10) further includes a built-in self-test circuit (12) connected to receive a self-test select signal. This embedded self-test circuit 12 may be operated to generate an internal self-test signal based on the operation and testing of the memory array 26 when the memory device 10 is in the self-test mode. The data buffer 28 is connected to receive an internal self test signal and a monitor mode signal. The data buffer 28 is operable to connect an internal self-test signal to a terminal of the memory device 10 to provide an external self-test signal at the memory device 10 when the memory device 10 is in self-do. The monitored internal self-test signal can be used to verify the operation of the embedded self-test circuit 12. [ The monitored self-test signal can also be used to test other memory devices in test mode.
机译:本发明的集成电路存储装置10具有自检监视模式。存储设备10包括具有多个存储单元的存储阵列26。存储设备(10)还包括内置的自检电路(12),该电路被连接以接收自检选择信号。当存储器装置10处于自测试模式时,可以基于存储器阵列26的操作和测试来操作该嵌入式自测试电路12以生成内部自测试信号。数据缓冲器28被连接以接收内部自测试信号和监视模式信号。数据缓冲器28可操作以将内部自测试信号连接到存储设备10的端子,以在存储设备10处于自做状态时在存储设备10处提供外部自测试信号。监视的内部自测试信号可用于验证嵌入式自测试电路12的操作。[监视的自测试信号也可用于在测试模式下测试其他存储设备。

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