LOCK MAINTAINING AND CACHE CONSISTENCY MAINTAINING CONTROLLER TO THE DATA UNDER LOCKING OPERATION ON MULTI-PROCESSOR SYSTEM

摘要

The present invention relates to a lock guarantee and a cache coincidence guarantee device in a multiprocessor system. The present invention relates to a lock guarantee and cache coincidence guarantee device in a multiprocessor system. A first to second latch means for storing and outputting a lock address being stored from a bus, and a first input indicating whether or not the output value of the first latch means and the lock address value currently being executed on the bus are compared with each other. A first latch comparing means for outputting a latch matching signal, a second latch matching signal indicating whether or not the output value of the second latching means and the lock address value currently being executed on the bus are compared, and outputting the same; Equation of the processor module requesting the second latch comparison means and an ongoing cycle on the bus Identifier comparison means for outputting an identifier matching signal that compares a source source identifier with a unique identifier of its own identifier to indicate whether it is the same or not, and checks whether the type of a cycle in progress on the bus is a lock related type or not. Transmission type comparison means for outputting a transmission type cache signal indicating a cycle and an interlock read signal indicating a lock read related cycle and an interlock write signal indicating a lock write related cycle, the identifier matching signal, the interlock read signal, and the A memory response signal indicating the interlock write signal and the memory module state, and a processor snoop non-response signal indicating the success of the snooping by indicating the state of the processor module and the bus grant signal indicating that the cycle in progress on the bus has been completed successfully. Control means for receiving a bus signal and the bus clock and outputting a first request signal and a second request signal indicating that the cycle is canceled successfully on the call and the bus; and the first request signal and the bus clock. A first lock notification means for receiving a first lock generation signal indicating that a lock cycle is currently in progress, and receiving a second request signal and the bus clock to receive a second lock progress signal indicating that a lock related cycle is in progress. A processor for prohibiting snooping by receiving a second lock notification means for outputting the first lock progress signal, the second lock progress signal, the first latch match signal, the second latch match signal, and the transfer type cache signal; Since it includes a processor snoop non-response signal generating means for outputting a snoop non-response signal, Effect lies in that a logic circuit is very simple to configure the logic circuit by using the state transition diagram.