Dynamic-Latch Circuit Prevents Timing Hazards

摘要

The present invention seeks to provide a dynamic-latch circuit that prevents timing hazards that can achieve a stable output independent of timing glitches to prevent static-1 hazards that may be caused by glitches (0). To this end, the dynamic-latch circuit of the present invention performs a first logical multiplication of a data signal and a clock signal, a second logical multiplication of the inverted clock signal and a feedback output terminal signal, and a third logical multiplication of the data signal and the output terminal signal. And a logic circuit for ORing both the first logical result, the second logical result, and the third logical result, and outputting the result to the output terminal.