Self-invalidating apparatus and method for reducing coherence overhead of multiple processes

摘要

SUMMARY OF THE INVENTION The present invention is directed to an apparatus and method for reducing cache coherence overhead in a shared bus multiprocessor device that requires an explicitly disclosed shared bus invalidation transaction to reduce invalidation traffic on a shared bus to an individual processor node Characterized in that it comprises a magnetic invalidation means for invalidating the local cache blocks, and wherein the method is an extension of the write invalidation control means applicable to the local processor node, and a hardware-dependent self-negating means, and a conservative read sniffering means for reducing cache miss and read misses due to incorrect prediction of magnetic invalidation by the magnetic invalidation means, thereby reducing coherency traffic of the shared bus multiprocessor device To The method comprising the steps of:;According to the present invention, invalidation traffic on the shared bus is reduced, and cache blocks are locally invalidated without requiring explicit invalidation shared bus transactions.