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Method for forming capacitor in analog process using chemical vapor deposition method

机译:利用化学气相沉积法在模拟过程中形成电容器的方法

摘要

The present invention relates to a method for forming a capacitor having an analog structure of a semiconductor device, the method comprising: preparing a substrate having an insulating oxide film formed on a top surface of a semiconductor substrate and having an ion-implanted polycrystalline silicon layer formed thereon by etching; Depositing a silicon dioxide film on the upper surface of the substrate on which the polycrystalline silicon layer is formed by chemical vapor deposition; Stacking a polycrystalline silicon layer on the upper surface of the stacked silicon dioxide film and implanting impurities; Forming an impurity-doped polycrystalline silicon layer by patterning the impurity-implanted polycrystalline silicon layer to form an analog circuit; The present invention provides a method of forming a capacitor in an analogue process using a chemical vapor deposition method, wherein the polycrystalline silicon residue generated in the second polycrystalline silicon layer etching process is not generated. Therefore, an appearance defect, an electrical short circuit, There is an advantage of improving defective improvement.
机译:本发明涉及一种形成具有半导体器件的模拟结构的电容器的方法,该方法包括:制备衬底,该衬底具有在半导体衬底的顶表面上形成的绝缘氧化物膜并且具有离子注入的多晶硅层。通过蚀刻在其上形成;通过化学气相沉积在形成有多晶硅层的基板的上表面上沉积二氧化硅膜;在堆叠的二氧化硅膜的上表面上堆叠多晶硅层并注入杂质;通过图案化注入杂质的多晶硅层以形成模拟电路来形成杂质掺杂的多晶硅层;本发明提供一种使用化学气相沉积法在模拟过程中形成电容器的方法,其中不产生在第二多晶硅层蚀刻过程中产生的多晶硅残余物。因此,具有外观不良,电气短路,改善不良的优点。

著录项

  • 公开/公告号KR980011755A

    专利类型

  • 公开/公告日1998-04-30

    原文格式PDF

  • 申请/专利权人 김광호;

    申请/专利号KR19960030189

  • 发明设计人 김범석;

    申请日1996-07-24

  • 分类号H01L21/20;

  • 国家 KR

  • 入库时间 2022-08-22 02:45:28

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