Counter circuit using a counter from the johnson - type and using same

摘要

A counter circuit includes Johnson-type counters (JC₁ ∼ JCm) of m stages, each counter including a plurality of flip-flops (FF₁₁ ∼ FF1N1,FF₂₁ ∼ FF2N2,... ..., FFm1 ∼ FFmNm) connected in a cascade connection, each flip-flop receiving a clock signal (CLK) at a respective clock input end (C). In the constitution, signals at respective output ends (Q) of flip-flops in a (k-1)-th stage counter are simultaneously input to respective clock input ends (C) of flip-flops in each counter of a k-th stage and more. As a result, it is possible to obtain a signal having an arbitrary ratio of freguency division with high speed, while relatively simplifying the circuit constitution.