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DIGITALLY CONTROLLED JITTER DAMPING DEVICE WITH DIGITAL FREQUENCY SYNTHETIZER
DIGITALLY CONTROLLED JITTER DAMPING DEVICE WITH DIGITAL FREQUENCY SYNTHETIZER
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机译:具有数字频率合成器的数字控制抖动抑制装置
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摘要
A circuit for attenuating phase jitter on an incoming clock signal includes a digital frequency synthesizer, and a phase lock loop including a phase detector. The digital phase detector compares the phase relationship between an incoming signal and a clock signal generated by the digitally controlled frequency synthesizer and produces an output signal proportional to the phase difference. The output signal comprises both a direction indicator and a magnitude indicator for controlling the digitally controlled frequency synthesizer. One of a plurality of phases of a voltage controlled oscillator (VCO) are selected in response to the output signal to alter the frequency of the clock signal.
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