Restoration of pulse width in buffers with unequal leading and trailing edge propagation delays

摘要

The PMOS and NMOS transistors in the cascaded inverters IV11-IV15 are dimensioned so that the delay of the leading edge of an input pulse is minimised at the expense of increased trailing edge delay. To reduce trailing edge delay, the trailing edge of the input pulse is detected by circuit 31, which outputs a short pulse on node N7. This pulse propagates through the inverter string IV16-IV19 and actuates the speed-up transistors MP1-MP3 and MN1-MN2 to assist charging or discharging respectively of nodes in the main inverter string IV11-IV15. Alternatively, the short pulse may be delayed and applied to a logic gate at the end of the inverter string to end the output pulse (figure 5). The circuit may be used in memory input buffers.