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Data processing with energy-efficient, multi-divided module memory architectures
Data processing with energy-efficient, multi-divided module memory architectures
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机译:采用高效节能的多模块内存架构进行数据处理
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摘要
A memory architecture (11,12) includes an address bus and a plurality of address decoders (15). Each address decoder has an input which is selectively connectable to and disconnectable from the address bus.
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