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Transmission system and multiplexing/demultiplexing equipment involving a justifiable bit stream

机译:涉及合理比特流的传输系统和复用/解复用设备

摘要

For this system and for this equipment there has been provided a phase alignment device (30) which has an access for input data (50) applied to an access (51) at a rate of a first clock signal, and an access (70) for producing at the rate of a second clock signal applied to an access (71) a justifiable data stream, in which stream bits can be inserted or deleted. The data are written and read in and from a common memory (60) by means of a write counter (55) and a read counter (80), respectively. A comparing element (90) measures the difference of the contents of said counters (55) and (80). With each variation of this difference, intermediate steps are added with the elements (95), (97) and (98), so that the means (92) controlling the justification can be formed by a sigma-delta modulator which has a 0.5 threshold.
机译:对于该系统和该设备,已经提供了相位对准设备(30),该相位对准设备(30)具有以第一时钟信号的速率对施加到接入(51)的输入数据(50)的接入,以及接入(70)。用于以施加到访问(71)的第二时钟信号的速率产生可调整的数据流,其中可以插入或删除流比特。分别通过写计数器(55)和读计数器(80)将数据写入和从公共存储器(60)中读取。比较元件(90)测量所述计数器(55)和(80)的内容之差。随着该差异的每个变化,在中间步骤中添加元素(95),(97)和(98),以便可以通过具有0.5阈值的sigma-delta调制器来形成控制对齐的装置(92) 。

著录项

  • 公开/公告号US5703915A

    专利类型

  • 公开/公告日1997-12-30

    原文格式PDF

  • 申请/专利权人 LUCENT TECHNOLOGIES INC.;

    申请/专利号US19950526018

  • 发明设计人 ALAIN VERGNES;PATRICK ALBERT;

    申请日1995-09-08

  • 分类号H04J3/06;H04L7/04;

  • 国家 US

  • 入库时间 2022-08-22 02:40:32

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