Parallel processing system for time division multiplex data transfer including read/write dual port memory accessible to bus and digital signal processor during opposite phases of clock

摘要

Disclosed is a multiprocessor system made up of several processing nodes linked by a time division multiplexed (TDM) bus to form a synchronous system. According to one embodiment, each processing node includes a digital signal processing (DSP) element, a dual port memory element and a memory control element in an integrated structure. Each memory element is segmented into four quarters. The first two are for read operations by the DSP element and write operations by the bus. However, the DSP element and the bus can only access any given segment during opposite phases of a frame clock signal. Additionally, each node is assigned an exclusive identification code whereby each node can post data to a memory element of another node.PPAccording to another embodiment, the various elements of each node are combined in various integrated structures.