Semiconductor memory having a refresh operation cycle and operating at a high speed and reduced power consumption in a normal operation cycle

摘要

An ordinary read/write operation (normal operation) and a refresh operation are separated from one another and the number of read amplification circuits or, in other words, the number of sense amplifiers operating during the normal operation is made smaller than that during the refresh operation. Accordingly, a bit line charge/discharge current during the normal operation can be reduced.