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Cache memory system having multiple caches with each cache mapped to a different area of main memory to avoid memory contention and to lessen the number of cache snoops

机译:具有多个高速缓存的高速缓存存储系统,每个高速缓存映射到主内存的不同区域,以避免内存争用并减少高速缓存监听的次数

摘要

A cache memory system includes a plurality of processors and a plurality of caches respectively assigned to the plurality of processors. Each cache is mapped to a different region of the main memory, so that memory contention is lessened to a great extent. Based on a memory address received by a cache, the cache compares the memory address to its assigned region of addresses. If the memory address falls within the assigned region for the cache, the cache then examines its contents as to determine if there is an address hit in the cache. If the memory address does not fall within the assigned region for the cache, the cache does not examine its contents to determine if there is an address hit in the cache, since an address hit is not possible in that case.
机译:高速缓冲存储器系统包括多个处理器和分别分配给多个处理器的多个高速缓存。每个高速缓存都映射到主内存的不同区域,因此可以大大减少内存争用。基于高速缓存接收的内存地址,高速缓存将内存地址与其分配的地址区域进行比较。如果内存地址落在为高速缓存分配的区域内,则高速缓存将检查其内容,以确定高速缓存中是否存在命中的地址。如果内存地址不在高速缓存的分配区域内,则高速缓存不会检查其内容以确定高速缓存中是否有地址命中,因为在这种情况下,地址命中是不可能的。

著录项

  • 公开/公告号US5737564A

    专利类型

  • 公开/公告日1998-04-07

    原文格式PDF

  • 申请/专利权人 ADVANCED MICRO DEVICES INC.;

    申请/专利号US19950463271

  • 发明设计人 SALIM A. SHAH;

    申请日1995-06-05

  • 分类号G06F12/10;

  • 国家 US

  • 入库时间 2022-08-22 02:39:52

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