DRAM with edge sense amplifiers which are activated along with sense amplifiers internal to the array during a read cycle

摘要

A staggered bitline sense amplifier architecture utilizes a circuit to simulate the effect of a memory cell on each of the edge sense amplifiers not selected for connection to an activated memory cell, thereby to allow the edge sense amplifiers to be activated simultaneously with the sense amplifiers internal to the memory array without the danger of burning out the edge sense amplifiers. This structure eliminates the address decoding circuitry commonly associated with the edge sense amplifiers used in staggered shared bitline sense amplifier architectures, thereby decreasing the complexity and reducing the chip size of such memory arrays.