System and method for altering the clock frequency to a logic controller controlling a logic device running at a fixed frequency slower than a computer system running the logic device

摘要

A system for altering a clock frequency to a logic controlling device that controls logic which runs at a fixed frequency slower than a frequency of a computer system running the logic. The system speeds up the clock signal to a logic controller when the logic controller is arbitrating between different operational requests. When the logic controller acknowledges a specific operational request, the clock controller immediately slows the clock signal down in order to allow a command strobe length that the logic device executing a specific operation request requires.