Floating point multiplier with reduced critical paths using delay matching techniques

摘要

A floating point multiplier with partial support for subnormal operands and results uses radix-4 or modified Booth encoding and a binary tree of 4:2 compressors to generate the 53×53 double- precision product. Delay matching techniques in the binary tree stage and in the final addition stage reduce cycle time. Improved rounding and sticky-bit generating techniques further reduce area and timing. The overall multiplier has a latency of 3 cycles, a throughput of 1 cycle, and a cycle time of 6.0 ns.