FLOATING POINT MULTIPLIER REDUCING CRITICAL PATH BY UTILIZING DELAY MATCHING TECHNIQUE AND CALCULATING METHOD THEREFOR

摘要

PROBLEM TO BE SOLVED: To improve operation speed by reducing the mutual connection part between multipliers. ;SOLUTION: A device including an integrated double precision floating point multiplication circuit is provided with plural input signal terminals, plural output signal terminals and a binary tree adder array. The binary tree adder array is connected with input terminal and output terminal for inputting plural multiplication data and plural data to be multiplied via plural input signal terminals and for outputting the product data corresponding to the data via plural output signal terminals. The binary tree adder array is integrated in a regular structure provided with plural edges and the location adjustment of the array along the first edge of the plural edges is performed, and the plural input signal terminals and output signal terminals are arranged along the second edge of the plural edges.;COPYRIGHT: (C)1997,JPO