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Precision time interval division with digital phase delay lines
Precision time interval division with digital phase delay lines
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机译:使用数字相位延迟线进行精确的时间间隔划分
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摘要
A time interval division circuit that generates a delayed signal that is a precise integer fraction of the clock cycle. A digital delay loop including a digital delay line is locked to the clock cycle and controls a second digital delay line. The delay line characteristics determine the fraction of the clock cycle generated. The time interval division circuit tracks the clock cycle, rather than on-chip circuit delays as conventional delay lines.
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