DETECTION OF UNDER-ETCHED VIA OR SPACE, OR OF UNDERPOLISHED PORTION IN WAFER STACK

摘要

PROBLEM TO BE SOLVED: To optically inspect vias in a wafer stack by allowing a dielectric layer disposed on a metal layer to have a plurality of vias etched with an etchant, which is configured to etch the metal layer at a faster rate than the dielectric layer. ;SOLUTION: A wafer stack 200 has a plurality of bias 210, 212, 214, 216, 218, and 220 etched in a dielectric layer 208 disposed on a conductor layer 206. The conductor layer is made of, for example, a metal. For this structure, since vias 210, 214, 216, and 220 are under-etched, some dielectric substances of the dielectric layer 208 exist between the vias 210, 214, 216, and 220 and the metal layer 206. As an etchant, one which has a higher etching selectivity of the metal layer 206 with respect to the dielectric layer 208 is selected. In other words, the etchant etches the metal layer 206 at a substantially faster rate than the dielectric layer 208.;COPYRIGHT: (C)1999,JPO