CMOS SEMICONDUCTOR INTEGRATED CIRCUIT, INFORMATION PROCESSOR AND DESIGN SUPPORT SYSTEM

摘要

PROBLEM TO BE SOLVED: To ensure a timing margin of signal transmission even with a long wiring, improve a circuit speed and reduce noise emission by making a wiring between the functional circuit blocks of a CMOS semiconductor a differential transmission line. ;SOLUTION: A cell is provided as a circuit element of a logic gate, etc., composed of a plurality of MOS transistors, and a differential signal transmission cell (differential driver) 12a, a differential signal, transmission cell (differential receiver) 12b and single end cells 13a and 13b are provided. The differential driver 12a is provided with positive and negative logical outputs as output terminals, and the differential receiver 12b is provided with a positive logic (+) and a negative logic (-) as input terminals. An inner wiring 14a transmits an output signal from the cell 13a to the differential driver 12a. An inner wiring 14b transmits an input signal to the differential receiver 12b to the cell 13b. Respective inner wirings 14a and 14b becomes a wiring between the cells in the same circuit block. Outer wirings 151 and 152 transmit a differential signal via a wiring between functional blocks A and B.;COPYRIGHT: (C)1999,JPO