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The PIC device which is produced with the production manner and this manner of the PIC (power integrated circuit) device

机译:用PIC(功率集成电路)器件的生产方式和这种方式生产的PIC器件

摘要

A deep diffusion of the back-gate region provided in a self-aligned manner with respect to the gate electrode is necessary in a DMOS transistor for obtaining a sufficiently high punch-through voltage between source and drain. The combination of a comparatively heavy back-gate implantation and a light source implantation and a heavy source implantation with spacer on the gate electrode, and the use of interstitial diffusion and accelerated diffusion owing to crystal damage render it possible to carry out said diffusion of the back-gate region at a comparatively low temperature, for example below 950 DEG C. This renders it possible to integrate a DMOST into, for example, standard VLSI CMOS where first delta Vth and channel-profile implantations are carried out, and subsequently the poly gates are provided, which means that a diffusion step at a temperature above 1,000 DEG C. of long duration is no longer allowed. The effect may be enhanced in that the doping of the back-gate region is increased during the p-type LDD implantation of a p-channel MOS and/or the p-type well implantation of an n-channel MOS.
机译:为了在源极和漏极之间获得足够高的穿通电压,在DMOS晶体管中需要以相对于栅电极自对准的方式提供的背栅区域的深度扩散。相对较重的背栅注入和光源注入以及在栅电极上具有间隔物的较重源注入的结合,以及由于晶体损坏而导致的间隙扩散和加速扩散的使用,使得可以进行所述扩散。背栅区域处于相对较低的温度下,例如低于950℃。这使得可以将DMOST集成到例如标准VLSI CMOS中,在该标准VLSI CMOS中首先进行δVth和沟道轮廓注入,然后进行多晶硅提供了门,这意味着不再允许在高于1000℃的温度下长时间的扩散步骤。通过在p沟道MOS的p型LDD注入和/或n沟道MOS的p型阱注入期间增加背栅区域的掺杂,可以增强效果。

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