LOGIC CIRCUIT, LOGIC CIRCUIT DESIGN DEVICE, METHOD FOR DESIGNING CIRCUIT, AND COMPUTER READABLE RECORDING MEDIUM WITH DESIGN PROGRAM FOR LOGIC CIRCUIT RECORDED

摘要

PROBLEM TO BE SOLVED: To shorten a delay time in a path running through VDDL cells by connecting only a plurality of first cells to the output of an amplifying means for amplifying the second supply voltage which is lower than the first one to the first supply voltage. ;SOLUTION: A plurality of first cells G3, G5, G8 which are driven by the first supply voltage VDDH and a plurality of second cells G2, G4, G6, G7 which are driven by the second supply voltage VDDL which is lower than the first one VDDH are located and the second supply voltage VDDL is amplified to the first supply voltage VDDH by means of a level converter LC 101 which is an amplifying means. At that time, only the first cells G3, G5, G8 are connected to the output of the level converter LC 101. By this method, a delay time in a path running through the VDDL cells G2, G4, G6, G7 can be shortened.;COPYRIGHT: (C)1999,JPO