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In multiprocessor system the deadlock avoidance circuit
In multiprocessor system the deadlock avoidance circuit
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机译:在多处理器系统中,避免死锁的电路
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摘要
PURPOSE:To prevent the double generation of a command even though a local bus is interrupted to evade the deadlocks by securing a constitution where a bus arbiter returns the bus right to a processor that produced a request after a using request is produced from a local bus request assuring circuit and transferred. CONSTITUTION:An operation is carried out to local bus 13 with a command given from a buffer 123. When a request is transferred to a buffer 124 of a bus interface circuit 12 from the bus 13, a bus open request RQi disappears. Thus a grant GRi is produced to a processor 15 based on the information held by a bus right return assuring circuit 111 of a bus arbiter 11. As a result, a command is produced again from the processor 15. In this case, the registration is suppressed for the command produced again from the processor 15 to the buffer 124 with the output of a re-registration suppressing circuit 122. Thus the double registration of a command is prevented.
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