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In multiprocessor system the deadlock avoidance circuit

机译:在多处理器系统中,避免死锁的电路

摘要

PURPOSE:To prevent the double generation of a command even though a local bus is interrupted to evade the deadlocks by securing a constitution where a bus arbiter returns the bus right to a processor that produced a request after a using request is produced from a local bus request assuring circuit and transferred. CONSTITUTION:An operation is carried out to local bus 13 with a command given from a buffer 123. When a request is transferred to a buffer 124 of a bus interface circuit 12 from the bus 13, a bus open request RQi disappears. Thus a grant GRi is produced to a processor 15 based on the information held by a bus right return assuring circuit 111 of a bus arbiter 11. As a result, a command is produced again from the processor 15. In this case, the registration is suppressed for the command produced again from the processor 15 to the buffer 124 with the output of a re-registration suppressing circuit 122. Thus the double registration of a command is prevented.
机译:目的:通过确保一种构造,即在本地总线产生使用请求后,总线仲裁器将总线权返回给产生请求的处理器,以防止即使中断了本地总线以逃避死锁,也避免了重复生成命令请求保证电路并转移。构成:使用来自缓冲器123的命令对本地总线13进行操作。当请求从总线13传输到总线接口电路12的缓冲器124时,总线打开请求RQi消失。因此,基于总线仲裁器11的总线权利返回保证电路111所保持的信息,将许可GRi产生给处理器15。结果,再次从处理器15产生命令。在这种情况下,注册是通过重新注册抑制电路122的输出,针对从处理器15再次生成到缓冲器124的命令来抑制该命令。因此,防止了命令的双重注册。

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