The present invention provides solid state power controller governance circuitry which includes a power level select circuit(150, 152, 154 155, 156), a power level transition circuit (280), a controlled power limiting circuit (300, 320, 340, 380, 202), and apower level transition reset circuit (280, 390). The circuits together provide an analog voltage or resistance signal for input to astandard power controller device that allows not only for the efficient control of the power level in the power level in the powereddevice, but additionally provides for controlled power limiting to the powered device when changes in the function of thepowered device are initiated or when other conditions warrant rapid power limiting to the device. The circuits also provide meanswhereby the powered device may be appropriately re-powered from a zero state after controlled power limiting has occured.Together the circuits of the present invention provide a means whereby powered devices may be efficiently, smoothly, and safelyoperated by standard power motor controller circuits.
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