Vertical bipolar semiconductor power transistor with an interdigitised geometry, with optimisation of the base-to-emitter potential difference

摘要

The transistor (20) comprises: an epitaxial layer (22, 25) with a first conductivity type; a base buried region (23) with a second conductivity type; a sinker base region (26) with the second conductivity type, which extends from the main surface (25a) to the buried base region, and delimits, together with the base buried region, emitter fingers (27) in the epitaxial layer; an emitter buried region (24) with the first conductivity type and a doping level which is higher than that of the epitaxial layer, said emitter buried region (24) being embedded in the epitaxial layer in a position adjacent to the base buried region; and a sinker emitter region (28) having the first conductivity type and a doping level which is higher than that of the epitaxial layer and extending from the main surface to the emitter buried region inside the emitter fingers. The buried and sinker emitter regions delimit in each finger pairs of sections (24d, 28a) which are mutually spaced and delimit between one another a central region (25b) of epitaxial layer. The sinker emitter region sections (28a) of a finger extend in the vicinity of mutually facing edges of the emitter buried region sections (24d).