MULTIPLE PARALLEL DIGITAL DATA STREAM CHANNEL CONTROLLER ARCHITECTURE

摘要

A multiple data stream channel controller (26) providing demand driven transport of multiple data streams concurrently in real time through a peripheral data channel (41) coupled between a general purpose processor system (12) and a special purpose processor system (36). The controller comprises a first bus master interface (24) coupled to a general purpose processor system bus (20), a second bus master interface coupled to a special purpose processor system bus (30), a segmentable buffer memory (not shown) and a controller (26) that directs the transfer of data segments between the first and second bus master interfaces via the segmentable buffer memory. The controller is responsive to signals provided by the special purpose processor bus (30) to request transfer of successive data segments from respective data streams staged in the segmentable buffer memory. The controller moderates the transfer of successive data segments of the respective data streams via the first bus master interface (24) to the segmentable buffer memory.