Multiple parallel digital data stream channel controller architecture

摘要

(57) [Abstract] multiplexed data stream channel controller (26), required in real-time simultaneously over a (41) near a data channel coupled between the general purpose processor system special purpose processor system (12) and (36) to provide the transfer of data-driven multi-stream. Bus master and a second interface coupled bus master first interface that is coupled to the general-purpose processor system bus (20) and (24), a special purpose processor system bus (30), the controller, a partitionable buffer memory (not shown), and, and a (26) indicating controller direction of the data segments through a partitionable buffer memory between the master interface of the first and second. The controller is sensitive to the signal supplied special purpose processor bus (30) to request the transfer of data consecutive segments from the data stream of each of the stages in a partitionable buffer memory. Controller, to moderate the transfer to a partitionable buffer memory through the data contiguous segments of each data stream, the bus master interface of the first (24).