Method and system for bus arbitration in a multiprocessor system using simultaneous access of a variable width bus

摘要

Methods and systems are provided for enhanced bus access in a multiprocessor system with multiple processors coupled to system memory via a common wide bus. The common wide bus may be divided into multiple sub-buses, which may be accessed individually or in groups by a selected processor, or individual sub-buses may be accessed simultaneously by multiple processors. Each processor is responsive to one or more pending transactions to request bus arbitration logic for a maximum allowed number of sub-buses, /RTI If the number of authorized subbuses for a particular processor is equal to the number of pending transactions for that processor, all pending transactions are performed in parallel on the individual subbuses. If the number of authorized sub-buses is less than the number of pending transactions, pending transactions are performed in priority order. Finally, if the number of granted sub-buses is greater than the number of pending transactions, the selected transactions are performed in parallel on the sub-bus, greatly speeding up their transactions.