METHOD AND SYSTEM FOR BUS ARBITRATION IN A MULTIPROCESSOR SYSTEM UTILIZING SIMULTANEOUS VARIABLE-WIDTH BUS ACCESS

摘要

A method and system for enhanced bus arbitration in a multiprocessor system havingmultiprocessors coupled to a system memory via a common wide bus. The common widebus is subdivided into multiple sub-buses which may be accessed individually or in groupsby a selected processor, or individual sub-buses may be accessed by multiple processorssimultaneously. In response to one or more pending transactions, each processor outputsa request to bus arbitration logic for a arbitration logic for a number of sub-buses. Amaximum number of sub-buses is specified for each processor and the processors areprioritized. Each time a bus request is received from a processor, the number of requestedsub-buses is granted, if that number is equal to or less than the specified maximumnumber of sub-buses for that processor. If the requested number of sub-buses is greaterthan the specified maximum number of sub-buses for that processor the requested numberis granted if no other processor has issued a bus request.