The invalidation ranking decision logic device according to the status bits of the big team cache

摘要

The present invention relates to an invalidation ranking logic device according to a status bit of a big team cache, and more particularly, to an invalidation ranking logic device in which a processor unit (10) for performing various operations occurring inside a computer; A processor bus (20) for guiding a path so that the output signal can reach a destination when the processor unit (10) outputs a request signal; A bus interface (30) for latching a request signal generated on the processor bus (20) to extract only an address portion; A cache controller (40) for storing new information transmitted through the bus interface (30) in a cache (50); A cache 50 for storing new information such as an index address and a tag generated by the processor unit 10; When new information generated from the processor unit 10 is stored in the cache 50, the information stored in the cache is replaced with new information and stored in the new team buffer 70. At this time, A buffer controller 600 for controlling the number of the big-team caches so that the cache can be stored in the big-team buffer 70, an index address, a tag, and a status bit transmitted from the cache under the control of the buffer controller 60, The present invention relates to an invalidation ranking determining logic device according to a status bit of a big-team cache, and more particularly, to a write-Thereby improving the usability of the processor bus.